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A fast-settling folded-cascode CMOS operational amplifier
A fast-settling CMOS operational amplifier using the
folded-cascode topology has been designed. The design is
based on a theory developed by Yang et al for the optimum
settling time of two-pole systems for switched-capacitor
applications. The theory states that the two poles are
separated by a given factor in order to obtain a minimum
small-signal settling time. The design is achieved by
performing a complete small-signal analysis to gain a
better understanding of the frequency and time responses
of the folded-cascode op-amp. SPICE simulation results
are in good agreement with the theoretical predictions